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table 1. output current table. notes: 1. typical output current in a non-isolated buck converter. output power capability depends on respective output voltage. see key applications considerations section for complete description of assumptions, including fully discontinuous conduction mode (dcm) operation. 2. mostly discontinuous conduction mode. 3. continuous conduction mode. 4. packages: p: dip-8b, g: smd-8b, d: so-8c. lnk302/304-306 linkswitch-tn family lowest component count, energy-ef cient off-line switcher ic figure 1. typical buck converter application (see application examples section for other circuit con gurations). product highlights cost effective linear/cap dropper replacement ? lowest cost and component count buck converter solution ? fully integrated auto-restart for short-circuit and open loop fault protection ? saves external component costs ? lnk302 uses a simpli ed controller without auto-restart for very low system cost ? 66 khz operation with accurate current limit ? allows low cost off-the-shelf 1 mh inductor for up to 120 ma output current ? tight tolerances and negligible temperature variation ? high breakdown voltage of 700 v provides excellent input surge withstand ? frequency jittering dramatically reduces emi (~10 db) ? minimizes emi lter cost ? high thermal shutdown temperature (+135 c minimum) much higher performance over discrete buck and passive solutions ? supports buck, buck-boost and yback topologies ? system level thermal overload, output short-circuit and open control loop protection ? excellent line and load regulation even with typical con guration ? high bandwidth provides fast turn-on with no overshoot ? current limit operation rejects line ripple ? universal input voltage range (85 vac to 265 vac) ? built-in current limit and hysteretic thermal protection ? higher ef ciency than passive solutions ? higher power factor than capacitor-fed solutions ? entirely manufacturable in smd ecosmart ? ? extremely energy ef cient ? consumes typically only 50/80 mw in self-powered buck topology at 115/230 vac input with no load (opto feedback) ? consumes typically only 7/12 mw in yback topology with external bias at 115/230 vac input with no load ? meets california energy commission (cec), energy star, and eu requirements applications ? appliances and timers ? led drivers and industrial controls description linkswitch-tn is speci cally designed to replace all linear and capacitor-fed (cap dropper) non-isolated power supplies in the under 360 ma output current range at equal system cost while offering much higher performance and energy ef ciency. ? linkswitch-tn devices integrate a 700 v power mosfet, oscillator, simple on/off control scheme, a high voltage switched current source, frequency jittering, cycle-by-cycle current limit and thermal shutdown circuitry onto a monolithic ic. the start- up and operating power are derived directly from the voltage on the drain pin, eliminating the need for a bias supply and associated circuitry in buck or yback converters. the fully integrated auto-restart circuit in the lnk304-306 safely limits output power during fault conditions such as short-circuit or open loop, reducing component count and system-level load protection cost. a local supply provided by the ic allows use of a non-safety graded optocoupler acting as a level shifter to further enhance line and load regulation performance in buck and buck-boost converters, if required. november 2008 output current table 1 product 4 230 vac 15% 85-265 vac mdcm 2 ccm 3 mdcm 2 ccm 3 lnk302p/g/d 63 ma 80 ma 63 ma 80 ma lnk304p/g/d 120 ma 170 ma 120 ma 170 ma lnk305p/g/d 175 ma 280 ma 175 ma 280 ma lnk306p/g/d 225 ma 360 ma 225 ma 360 ma dc output wide range hv dc input pi-3492-111903 + + fb bp s d linkswitch-tn
2-2 rev. i 11/08 2 lnk302/304-306 figure 2a. functional block diagram (lnk302). pi-2367-021105 clock jitter oscillator 5.8 v 4.85 v source (s) s r q dc max bypass (bp) fault present + - v i limit leading edge blanking thermal shutdown + - drain (d) regulator 5.8 v bypass pin under-voltage current limit comparator feedback (fb) q 6.3 v reset auto- restart counter 1.65 v -v t clock figure 2b. functional block diagram (lnk304-306). pi-3904-020805 clock jitter oscillator 5.8 v 4.85 v source (s) s r q dc max bypass (bp) + - v i limit leading edge blanking thermal shutdown + - drain (d) regulator 5.8 v bypass pin under-voltage current limit comparator feedback (fb) q 6.3 v 1.65 v -v t
2-3 lnk302/304-306 3 rev. i 11/08 pin functional description drain (d) pin: power mosfet drain connection. provides internal operating current for both start-up and steady-state operation. bypass (bp) pin: connection point for a 0.1 f external bypass capacitor for the internally generated 5.8 v supply. feedback (fb) pin: during normal operation, switching of the power mosfet is controlled by this pin. mosfet switching is terminated when a current greater than 49 a is delivered into this pin. source (s) pin: this pin is the power mosfet source connection. it is also the ground reference for the bypass and feedback pins. linkswitch-tn functional description linkswitch-tn combines a high voltage power mosfet switch with a power supply controller in one device. unlike conventional pwm (pulse width modulator) controllers, linkswitch-tn uses a simple on/off control to regulate the output voltage. the linkswitch-tn controller consists of an oscillator, feedback (sense and logic) circuit, 5.8 v regulator, bypass pin under- voltage circuit, over-temperature protection, frequency jittering, current limit circuit, leading edge blanking and a 700 v power mosfet. the linkswitch-tn incorporates additional circuitry for auto-restart. oscillator the typical oscillator frequency is internally set to an average of 66 khz. two signals are generated from the oscillator: the maximum duty cycle signal (dc max ) and the clock signal that indicates the beginning of each cycle. the linkswitch-tn oscillator incorporates circuitry that introduces a small amount of frequency jitter, typically 4 khz peak-to-peak, to minimize emi emission. the modulation rate of the frequency jitter is set to 1 khz to optimize emi reduction for both average and quasi-peak emissions. the frequency jitter should be measured with the oscilloscope triggered at the falling edge of the drain waveform. the waveform in figure 4 illustrates the frequency jitter of the linkswitch-tn . feedback input circuit the feedback input circuit at the fb pin consists of a low impedance source follower output set at 1.65 v. when the current delivered into this pin exceeds 49 a, a low logic level (disable) is generated at the output of the feedback circuit. this output is sampled at the beginning of each cycle on the rising edge of the clock signal. if high, the power mosfet is turned on for that cycle (enabled), otherwise the power mosfet remains off (disabled). since the sampling is done only at the beginning of each cycle, subsequent changes in the fb pin voltage or current during the remainder of the cycle are ignored. 5.8 v regulator and 6.3 v shunt voltage clamp the 5.8 v regulator charges the bypass capacitor connected to the bypass pin to 5.8 v by drawing a current from the voltage on the drain, whenever the mosfet is off. the bypass pin is the internal supply voltage node for the linkswitch-tn . when the mosfet is on, the linkswitch-tn runs off of the energy stored in the bypass capacitor. extremely low power consumption of the internal circuitry allows the linkswitch-tn to operate continuously from the current drawn from the drain pin. a bypass capacitor value of 0.1 f is suf cient for both high frequency decoupling and energy storage. in addition, there is a 6.3 v shunt regulator clamping the bypass pin at 6.3 v when current is provided to the bypass pin through an external resistor. this facilitates powering of linkswitch-tn externally through a bias winding to decrease the no-load consumption to about 50 mw. bypass pin under-voltage the bypass pin under-voltage circuitry disables the power mosfet when the bypass pin voltage drops below 4.85 v. once the bypass pin voltage drops below 4.85 v, it must rise back to 5.8 v to enable (turn-on) the power mosfet. over-temperature protection the thermal shutdown circuitry senses the die temperature. the threshold is set at 142 c typical with a 75 c hysteresis. when the die temperature rises above this threshold (142 c) the power mosfet is disabled and remains disabled until the die temperature falls by 75 c, at which point it is re-enabled. current limit the current limit circuit senses the current in the power mosfet. when this current exceeds the internal threshold (i limit ), the pi-3491-120706 3a 3b fb d s bp s s s p package (dip-8b) g package (smd-8b) d package (so-8c) 8 5 7 1 4 2 3 d s fb s s bp 8 5 7 1 4 2 s 6 figure 3. pin con guration.
2-4 rev. i 11/08 4 lnk302/304-306 figure 5. universal input, 12 v, 120 ma constant voltage power supply using linkswitch-tn. power mosfet is turned off for the remainder of that cycle. the leading edge blanking circuit inhibits the current limit comparator for a short time (t leb ) after the power mosfet is turned on. this leading edge blanking time has been set so that current spikes caused by capacitance and recti er reverse recovery time will not cause premature termination of the switching pulse. auto-restart (lnk304-306 only) in the event of a fault condition such as output overload, output short, or an open loop condition, linkswitch-tn enters into auto- restart operation. an internal counter clocked by the oscillator gets reset every time the fb pin is pulled high. if the fb pin is not pulled high for 50 ms, the power mosfet switching is disabled for 800 ms. the auto-restart alternately enables and disables the switching of the power mosfet until the fault condition is removed. applications example a 1.44 w universal input buck converter the circuit shown in figure 5 is a typical implementation of a figure 4. frequency jitter. rtn 12 v, 120 ma 85-265 vac pi-3757-112103 fb bp s d linkswitch-tn c4 4.7 f 400 v c1 100 nf d4 1n4007 d3 1n4007 d1 uf4005 lnk304 d2 1n4005gp c2 100 f 16 v rf1 8.2 2 w r1 13.0 k 1% r3 2.05 k 1% l2 1 mh l1 1 mh 280 ma c5 4.7 f 400 v c3 10 f 35 v r4 3.3 k 12 v, 120 ma non-isolated power supply used in appliance control such as rice cookers, dishwashers or other white goods. this circuit may also be applicable to other applications such as night-lights, led drivers, electricity meters, and residential heating controllers, where a non-isolated supply is acceptable. the input stage comprises fusible resistor rf1, diodes d3 and d4, capacitors c4 and c5, and inductor l2. resistor rf1 is a ame proof, fusible, wire wound resistor. it accomplishes several functions: a) inrush current limitation to safe levels for recti ers d3 and d4; b) differential mode noise attenuation; c) input fuse should any other component fail short-circuit (component fails safely open-circuit without emitting smoke, re or incandescent material). the power processing stage is formed by the linkswitch-tn , freewheeling diode d1, output choke l1, and the output capacitor c2. the lnk304 was selected such that the power supply operates in the mostly discontinuous-mode (mdcm). diode d1 is an ultra-fast diode with a reverse recovery time (t rr ) of approximately 75 ns, acceptable for mdcm operation. for continuous conduction mode (ccm) designs, a diode with a t rr of 35 ns is recommended. inductor l1 is a standard off-the- shelf inductor with appropriate rms current rating (and acceptable temperature rise). capacitor c2 is the output lter capacitor; its primary function is to limit the output voltage ripple. the output voltage ripple is a stronger function of the esr of the output capacitor than the value of the capacitor itself. to a rst order, the forward voltage drops of d1 and d2 are identical. therefore, the voltage across c3 tracks the output voltage. the voltage developed across c3 is sensed and regulated via the resistor divider r1 and r3 connected to u1?s fb pin. the values of r1 and r3 are selected such that, at the desired output voltage, the voltage at the fb pin is 1.65 v. regulation is maintained by skipping switching cycles. as the output voltage rises, the current into the fb pin will rise. if this exceeds i fb then subsequent cycles will be skipped until the current reduces below i fb . thus, as the output load is reduced, more cycles will be skipped and if the load increases, fewer 600 020 68 khz 64 khz v drain time ( s) pi-3660-081303 500 400 300 200 100 0
2-5 lnk302/304-306 5 rev. i 11/08 figure 6a. recommended printed circuit layout for linkswitch-tn in a buck converter con guration using p or g package. cycles are skipped. to provide overload protection if no cycles are skipped during a 50 ms period, linkswitch-tn will enter auto-restart (lnk304-306), limiting the average output power to approximately 6% of the maximum overload power. due to tracking errors between the output voltage and the voltage across c3 at light load or no load, a small pre-load may be required (r4). for the design in figure 5, if regulation to zero load is required, then this value should be reduced to 2.4 k . key application considerations linkswitch-tn design considerations output current table data sheet maximum output current table (table 1) represents the maximum practical continuous output current for both mostly discontinuous conduction mode (mdcm) and continuous conduction mode (ccm) of operation that can be delivered from a given linkswitch-tn device under the following assumed conditions: 1) buck converter topology. 2) the minimum dc input voltage is 70 v. the value of input capacitance should be large enough to meet this criterion. 3) for ccm operation a krp* of 0.4. 4) output voltage of 12 vdc. 5) ef ciency of 75%. 6) a catch/freewheeling diode with t rr 75 ns is used for mdcm operation and for ccm operation, a diode with t rr 35 ns is used. 7) the part is board mounted with source pins soldered to a suf cient area of copper to keep the source pin temperature at or below 100 c. *krp is the ratio of ripple to peak inductor current. linkswitch-tn selection and selection between mdcm and ccm operation select the linkswitch-tn device, freewheeling diode and output inductor that gives the lowest overall cost. in general, mdcm + pi-3750-121106 c2 l1 l2 r1 r3 rf1 d3 d4 d2 d1 c1 c3 c5 c4 optimize hatched copper areas ( ) for heatsinking and emi. d s s fb bp s s linkswitch-tn ac input dc output figure 6b. recommended printed circuit layout for linkswitch-tn in a buck converter con guration using d package to bottom side of the board. ac input + dc output pi-4546-011807 optimize hatched copper areas ( ) for heatsinking and emi. s s s s bp fb d1 c2 r3 rf1 d3 d4 d2 r1 c1 c4 c5 c3 linkswitch-tn l2 l1 d
2-6 rev. i 11/08 6 lnk302/304-306 table 2. common circuit con gurations using linkswitch-tn. (continued on next page) topology basic circuit schematic key features high-side buck ? direct feedback 1. output referenced to input 2. positive output (v o ) with respect to -v in 3. step down ? v o < v in 4. low cost direct feedback (10% typ.) high-side buck ? optocoupler feedback 1. output referenced to input 2. positive output (v o ) with respect to -v in 3. step down ? v o < v in 4. optocoupler feedback - accuracy only limited by reference choice - low cost non-safety rated opto - no pre-load required 5. minimum no-load consumption low-side buck ? optocoupler feedback 1. output referenced to input 2. negative output (v o ) with respect to +v in 3. step down ? v o < v in 4. optocoupler feedback - accuracy only limited by reference choice - low cost non-safety rated opto - no pre-load required - ideal for driving leds low-side buck ? constant current led driver high-side buck boost ? direct feedback 1. output referenced to input 2. negative output (v o ) with respect to +v in 3. step up/down ? v o > v in or v o < v in 4. low cost direct feedback (10% typ.) 5. fail-safe ? output is not subjected to input voltage if the internal mosfet fails 6. ideal for driving leds ? better accuracy and temperature stability than low-side buck constant current led driver high-side buck boost ? constant current led driver v o v in pi-3751-121003 + + fb bp s d linkswitch-tn linkswitch-tn pi-3752-121003 + + bp fb d s v o v in linkswitch-tn pi-3753-111903 + + bp fb d s v o v in linkswitch-tn pi-3754-112103 + + bp fb d s v in i o r = v f v f i o v o v in pi-3755-121003 + + fb bp s d linkswitch-tn r sense = r sense 300 2 k 2 v i o i o 100 nf 10 f 50 v v in pi-3779-120803 + fb bp s d linkswitch-tn
2-7 lnk302/304-306 7 rev. i 11/08 table 2 (cont). common circuit con gurations using linkswitch-tn. topology basic circuit schematic key features low-side buck boost ? optocoupler feedback 1. output referenced to input 2. positive output (v o ) with respect to +v in 3. step up/down ? v o > v in or v o < v in 4. optocoupler feedback - accuracy only limited by reference choice - low cost non-safety rated opto - no pre-load required 5. fail-safe ? output is not subjected to input voltage if the internal mosfet fails provides the lowest cost and highest ef ciency converter. ccm designs require a larger inductor and ultra-fast (t rr 35 ns) freewheeling diode in all cases. it is lower cost to use a larger linkswitch-tn in mdcm than a smaller linkswitch-tn in ccm because of the additional external component costs of a ccm design. however, if the highest output current is required, ccm should be employed following the guidelines below. topology options linkswitch-tn can be used in all common topologies, with or without an optocoupler and reference to improve output voltage tolerance and regulation. table 2 provide a summary of these con gurations. for more information see the application note ? linkswitch-tn design guide. component selection referring to figure 5, the following considerations may be helpful in selecting components for a linkswitch-tn design. freewheeling diode d1 diode d1 should be an ultra-fast type. for mdcm, reverse recovery time t rr 75 ns should be used at a temperature of 70 c or below. slower diodes are not acceptable, as continuous mode operation will always occur during startup, causing high leading edge current spikes, terminating the switching cycle prematurely, and preventing the output from reaching regulation. if the ambient temperature is above 70 c then a diode with t rr 35 ns should be used. for ccm an ultra-fast diode with reverse recovery time t rr 35 ns should be used. a slower diode may cause excessive leading edge current spikes, terminating the switching cycle prematurely and preventing full power delivery. fast and slow diodes should never be used as the large reverse recovery currents can cause excessive power dissipation in the diode and/or exceed the maximum drain current speci cation of linkswitch-tn . feedback diode d2 diode d2 can be a low-cost slow diode such as the 1n400x series, however it should be speci ed as a glass passivated type to guarantee a speci ed reverse recovery time. to a rst order, the forward drops of d1 and d2 should match. inductor l1 choose any standard off-the-shelf inductor that meets the design requirements. a ?drum? or ?dog bone? ?i? core inductor is recommended with a single ferrite element due to its low cost and very low audible noise properties. the typical inductance value and rms current rating can be obtained from the linkswitch-tn design spreadsheet available within the pi expert design suite from power integrations. choose l1 greater than or equal to the typical calculated inductance with rms current rating greater than or equal to calculated rms inductor current. capacitor c2 the primary function of capacitor c2 is to smooth the inductor current. the actual output ripple voltage is a function of this capacitor?s esr. to a rst order, the esr of this capacitor should not exceed the rated ripple voltage divided by the typical current limit of the chosen linkswitch-tn . feedback resistors r1 and r3 the values of the resistors in the resistor divider formed by r1 and r3 are selected to maintain 1.65 v at the fb pin. it is recommended that r3 be chosen as a standard 1% resistor of 2 k . this ensures good noise immunity by biasing the feedback network with a current of approximately 0.8 ma. feedback capacitor c3 capacitor c3 can be a low cost general purpose capacitor. it provides a ?sample and hold? function, charging to the output voltage during the off time of linkswitch-tn . its value should be 10 f to 22 f; smaller values cause poorer regulation at light load conditions. linkswitch-tn pi-3756-111903 + bp fb d s v o v in +
2-8 rev. i 11/08 8 lnk302/304-306 pre-load resistor r4 in high-side, direct feedback designs where the minimum load is <3 ma, a pre-load resistor is required to maintain output regulation. this ensures suf cient inductor energy to pull the inductor side of the feedback capacitor c3 to input return via d2. the value of r4 should be selected to give a minimum output load of 3 ma. in designs with an optocoupler the zener or reference bias current provides a 1 ma to 2 ma minimum load, preventing ?pulse bunching? and increased output ripple at zero load. linkswitch-tn layout considerations in the buck or buck-boost converter con guration, since the source pins in linkswitch-tn are switching nodes, the copper area connected to source should be minimized to minimize emi within the thermal constraints of the design. in the boost con guration, since the source pins are tied to dc return, the copper area connected to source can be maximized to improve heatsinking. the loop formed between the linkswitch-tn , inductor (l1), freewheeling diode (d1), and output capacitor (c2) should be kept as small as possible. the bypass pin capacitor c1 (figure 6) should be located physically close to the source (s) and bypass (bp) pins. to minimize direct coupling from switching nodes, the linkswitch-tn should be placed away from ac input lines. it may be advantageous to place capacitors c4 and c5 in-between linkswitch-tn and the ac input. the second recti er diode d4 is optional, but may be included for better emi performance and higher line surge withstand capability. quick design checklist as with any power supply design, all linkswitch-tn designs should be veri ed for proper functionality on the bench. the following minimum tests are recommended: 1) adequate dc rail voltage ? check that the minimum dc input voltage does not fall below 70 vdc at maximum load, minimum input voltage. 2) correct diode selection ? uf400x series diodes are recommended only for designs that operate in mdcm at an ambient of 70 c or below. for designs operating in continuous conduction mode (ccm) and/or higher ambients, then a diode with a reverse recovery time of 35 ns or better, such as the byv26c, is recommended. 3) maximum drain current ? verify that the peak drain current is below the data sheet peak drain speci cation under worst-case conditions of highest line voltage, maximum overload (just prior to auto-restart) and highest ambient temperature. 4) thermal check ? at maximum output power, minimum input voltage and maximum ambient temperature, verify that the linkswitch-tn source pin temperature is 100 c or below. this gure ensures adequate margin due to variations in r ds(on) from part to part. a battery powered thermocouple meter is recommended to make measurements when the source pins are a switching node. alternatively, the ambient temperature may be raised to indicate margin to thermal shutdown. in a linkswitch-tn design using a buck or buck boost converter topology, the source pin is a switching node. oscilloscope measurements should therefore be made with probe grounded to a dc voltage, such as primary return or dc input rail, and not to the source pins. the power supply input must always be supplied from an isolated source (e.g. via an isolation transformer).
2-9 lnk302/304-306 9 rev. i 11/08 absolute maximum ratings (1,5) drain voltage .................................. ................ -0.3 v to 700 v peak drain current (lnk302).................200 ma (375 ma) (2) peak drain current (lnk304).................400 ma (750 ma) (2) peak drain current (lnk305).................800 ma (1500 ma) (2) peak drain current (lnk306).................1400 ma (2600 ma) (2) feedback voltage .........................................-0.3 v to 9 v feedback current.............................................100 ma bypass voltage ..........................................-0.3 v to 9 v storage temperature .......................................... -65 c to 150 c operating junction temperature (3) ..................... -40 c to 150 c lead temperature (4) ........................................................260 c notes: 1. all voltages referenced to source, t a = 25 c. 2. the higher peak drain current is allowed if the drain to source voltage does not exceed 400 v. 3. normally limited by internal circuitry. 4. 1/16 in. from case for 5 seconds. 5. maximum ratings speci ed may be applied, one at a time, without causing permanent damage to the product. exposure to absolute maximum rating conditions for extended periods of time may affect product reliability. thermal impedance thermal impedance: p or g package: ( ja ) ........................... 70 c/w (3) ; 60 c/w (4) ( jc ) (1) ............................................... 11 c/w d package: ( ja ) ..................... .... 100 c/w (3) ; 80 c/w (4) ( jc ) (2) ............................................... 30 c/w notes: 1. measured on pin 2 (source) close to plastic interface. 2. measured on pin 8 (source) close to plastic interface. 3. soldered to 0.36 sq. in. (232 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 4. soldered to 1 sq. in. (645 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 7 (unless otherwise speci ed) min typ max units control functions output frequency f osc t j = 25 c average 62 66 70 khz peak-peak jitter 4 maximum duty cycle dc max s2 open 66 69 72 % feedback pin turnoff threshold current i fb t j = 25 c 30 49 68 a feedback pin voltage at turnoff threshold v fb 1.54 1.65 1.76 v drain supply current i s1 v fb 2 v (mosfet not switching) see note a 160 220 a i s2 feedback open (mosfet switching) see notes a, b lnk302/304 200 260 a lnk305 220 280 lnk306 250 310
2-10 rev. i 11/08 10 lnk302/304-306 parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 7 (unless otherwise speci ed) min typ max units control functions (cont.) bypass pin charge current i ch1 v bp = 0 v t j = 25 c lnk302/304 -5.5 -3.3 -1.8 ma lnk305/306 -7.5 -4.6 -2.5 i ch2 v bp = 4 v t j = 25 c lnk302/304 -3.8 -2.3 -1.0 lnk305/306 -4.5 -3.3 -1.5 bypass pin voltage v bp 5.55 5.8 6.10 v bypass pin voltage hysteresis v bph 0.8 0.95 1.2 v bypass pin supply current i bpsc see note d 68 a circuit protection current limit i limit (see note e) di/dt = 55 ma/ s t j = 25 c lnk302 126 136 146 ma di/dt = 250 ma/ s t j = 25 c 145 165 185 di/dt = 65 ma/ s t j = 25 c lnk304 240 257 275 di/dt = 415 ma/ s t j = 25 c 271 308 345 di/dt = 75 ma/ s t j = 25 c lnk305 350 375 401 di/dt = 500 ma/ s t j = 25 c 396 450 504 di/dt = 95 ma/ s t j = 25 c lnk306 450 482 515 di/dt = 610 ma/ s t j = 25 c 508 578 647 minimum on time t on(min) lnk302/304 280 360 475 ns lnk305 360 460 610 lnk306 400 500 675 leading edge blanking time t leb t j = 25 c see note f 170 215 ns thermal shutdown temperature t sd 135 142 150 c
2-11 lnk302/304-306 11 rev. i 11/08 parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 7 (unless otherwise speci ed) min typ max units circuit protection (cont.) thermal shutdown hysteresis t shd see note g 75 c output on-state resistance r ds(on) lnk302 i d = 13 ma t j = 25 c 48 55.2 t j = 100 c 76 88.4 lnk304 i d = 25 ma t j = 25 c 24 27.6 t j = 100 c 38 44.2 lnk305 i d = 35 ma t j = 25 c 12 13.8 t j = 100 c 19 22.1 lnk306 i d = 45 ma t j = 25 c 7 8.1 t j = 100 c 11 12.9 off-state drain leakage current i dss v bp = 6.2 v, v fb 2 v, v ds = 560 v, t j = 25 c lnk302/304 50 a lnk305 70 lnk306 90 breakdown voltage bv dss v bp = 6.2 v, v fb 2 v, t j = 25 c 700 v rise time t r measured in a typical buck converter application 50 ns fall time t f 50 ns drain supply voltage 50 v output enable delay t en see figure 9 10 s output disable setup time t dst 0.5 s auto-restart on-time t ar t j = 25 c see note h lnk302 ms lnk304-306 50 auto-restart duty cycle dc ar lnk302 % lnk304-306 6 not applicable not applicable
2-12 rev. i 11/08 12 lnk302/304-306 notes: a. total current consumption is the sum of i s1 and i dss when feedback pin voltage is 2 v (mosfet not switching) and the sum of i s2 and i dss when feedback pin is shorted to source (mosfet switching). b since the output mosfet is switching, it is dif cult to isolate the switching current from the supply current at the drain. an alternative is to measure the bypass pin current at 6 v. c. see typical performance characteristics section figure 14 for bypass pin start-up charging waveform. d. this current is only intended to supply an optional optocoupler connected between the bypass and feedback pins and not any other external circuitry. e. for current limit at other di/dt values, refer to figure 13. f. this parameter is guaranteed by design. g. this parameter is derived from characterization. h. auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency). figure 7. linkswitch-tn general test circuit. pi-3490-060204 50 v 50 v d fb s s s s bp s1 470 k s2 0.1 f 470 5 w pi-3707-112503 fb t p t en dc max t p = 1 f osc v drain (internal signal) figure 8. linkswitch-tn duty cycle measurement. figure 9. linkswitch-tn output enable timing.
2-13 lnk302/304-306 13 rev. i 11/08 200 300 350 400 250 0 0 4 28 6 101214161820 drain voltage (v) drain current (ma) pi-3661-071404 50 150 100 scaling factors: lnk302 0.5 lnk304 1.0 lnk305 2.0 lnk306 3.4 25 c 100 c typical performance characteristics figure 14. bypass pin start-up waveform. 1.1 1.0 0.9 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) breakdown voltage (normalized to 25 c) pi-2213-012301 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1.0 time (ms) pi-2240-012301 bypass pin voltage (v) 7 figure 10. breakdown vs. temperature. figure 12. current limit vs. temperature at normalized di/dt. figure 13. current limit vs. di/dt. figure 15. output characteristics. 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 junction temperature ( c) pi-2680-012301 output frequency (normalized to 25 c) figure 11. frequency vs. temperature. normalized di/dt pi-3710-071204 normalized current limit 1.0 1.2 1.4 0.8 0.6 0.4 0.2 0 123456 lnk302 lnk304 lnk305 lnk306 normalized di/dt = 1 55 ma/ s 65 ma/ s 75 ma/ s 95 ma/ s normalized current limit = 1 136 ma 257 ma 375 ma 482 ma temperature ( c) pi-3709-111203 current limit (normalized to 25 c) 1.0 1.2 1.4 0.8 0.6 0.4 0.2 0 -50 0 50 100 150 di/dt = 1 di/dt = 6 normalized di/dt
2-14 rev. i 11/08 14 lnk302/304-306 figure 16. c oss vs. drain voltage. drain voltage (v) drain capacitance (pf) pi-3711-071404 0 100 200 300 400 500 600 1 10 100 1000 lnk302 0.5 lnk304 1.0 lnk305 2.0 lnk306 3.4 scaling factors: typical performance characteristics (cont.) part ordering information linkswitch product family tn series number package identi er g plastic surface mount dip p plastic dip d plastic so-8c lead finish n pure matte tin (rohs compliant) g rohs compliant and halogen free (d package only) tape & reel and other options blank standard con gurations tl tape & reel, 1 k pcs minimum for g package. 2.5 k pcs for d package. not available for p package. lnk 304 g n - tl
2-15 lnk302/304-306 15 rev. i 11/08 notes: 1. package dimensions conform to jedec specification ms-001-ab (issue b 7/85) for standard dual-in-line (dip) package with .300 inch row spacing. 2. controlling dimensions are inches. millimeter sizes are shown in parentheses. 3. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 4. pin locations start with pin 1, and continue counter-clock- wise to pin 8 when viewed from the top. the notch and/or dimple are aids in locating pin 1. pin 6 is omitted. 5. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. lead width measured at package body. 7. lead spacing measured with the leads constrained to be perpendicular to plane t. .008 (.20) .015 (.38) .300 (7.62) bsc (note 7) .300 (7.62) .390 (9.91) .367 (9.32) .387 (9.83) .240 (6.10) .260 (6.60) .125 (3.18) .145 (3.68) .057 (1.45) .068 (1.73) .120 (3.05) .140 (3.56) .015 (.38) minimum .048 (1.22) .053 (1.35) .100 (2.54) bsc .014 (.36) .022 (.56) -e- pin 1 seating plane -d- -t- p08b dip-8b pi-2551-121504 d s .004 (.10) t e d s .010 (.25) m (note 6) .137 (3.48) minimum smd-8b pi-2546-121504 .004 (.10) .012 (.30) .036 (0.91) .044 (1.12) .004 (.10) 0 - 8 .367 (9.32) .387 (9.83) .048 (1.22) .009 (.23) .053 (1.35) .032 (.81) .037 (.94) .125 (3.18) .145 (3.68) -d- notes: 1. controlling dimensions are inches. millimeter sizes are shown in parentheses. 2. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 3. pin locations start with pin 1, and continue counter-clock- wise to pin 8 when viewed from the top. pin 6 is omitted. 4. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 5. lead width measured at package body. 6. d and e are referenced datums on the package body. .057 (1.45) .068 (1.73) (note 5) e s .100 (2.54) (bsc) .372 (9.45) .240 (6.10) .388 (9.86) .137 (3.48) minimum .260 (6.60) .010 (.25) -e- pin 1 d s .004 (.10) g08b .420 .046 .060 .060 .046 .080 pin 1 .086 .186 .286 solder pad dimensions
2-16 rev. i 11/08 16 lnk302/304-306 pi-4526-040207 d07c so-8c 3.90 (0.154) bsc notes: 1. jedec reference: ms-012. 2. package outline exclusive of mold flash and metal burr. 3. package outline inclusive of plating thickness. 4. datums a and b to be determined at datum plane h. 5. controlling dimensions are in millimeters. inch dimensions are shown in parenthesis. angles in degrees. 0.20 (0.008) c 2x 1 4 5 8 2 6.00 (0.236) bsc d 4 a 4.90 (0.193) bsc 2 0.10 (0.004) c 2x d 0.10 (0.004) c 2x a-b 1.27 (0.050) bsc 7x 0.31 - 0.51 (0.012 - 0.020) 0.25 (0.010) m c a-b d 0.25 (0.010) 0.10 (0.004) (0.049 - 0.065) 1.25 - 1.65 1.75 (0.069) 1.35 (0.053) 0.10 (0.004) c 7x c h o 1.27 (0.050) 0.40 (0.016) gauge plane 0 - 8 1.04 (0.041) ref 0.25 (0.010) bsc seating plane 0.25 (0.010) 0.17 (0.007) detail a detail a c seating plane pin 1 id b 4 + + + 4.90 (0.193) 1.27 (0.050) 0.60 (0.024) 2.00 (0.079) reference solder pad dimensions +
2-17 lnk302/304-306 17 rev. i 11/08 notes
2-18 rev. i 11/08 18 lnk302/304-306 notes
2-19 lnk302/304-306 19 rev. i 11/08 revision notes date c 1) released nal data sheet. 3/03 d 1) corrected minimum on time. 1/04 e 1) added lnk302. 8/04 f 1) added lead-free ordering information. 12/04 g 1) minor error corrections. 2) renamed feedback pin voltage parameter to feedback pin voltage at turnoff threshold and removed condition. 3/05 h 1) added so-8c package. 12/06 i 1) updated part ordering information section with halogen free 11/08
2-20 rev. i 11/08 20 lnk302/304-306 for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power inte grations. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a licens e under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in s igni? cant injury or death to the user. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, dpa-switch, peakswitch, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2006, power integrations, inc. 1. 2. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) room 1601/1610, tower 1 kerry everbright city no. 218 tianmu road west shanghai, p.r.c. 200070 phone: +86-21-6354-6323 fax: +86-21-6354-6325 e-mail: chinasales@powerint.com china (shenzhen) rm a, b & c 4th floor, block c, electronics science and technology bldg., 2070 shennan zhong rd, shenzhen, guangdong, china, 518031 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany rueckertstrasse 3 d-80336, munich germany phone: +49-89-5527-3910 fax: +49-89-5527-3920 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via de amicis 2 20091 bresso mi italy phone: +39-028-928-6000 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg. 2-12-11, shin-yokomana, kohoku-ku yokohama-shi kanagwan 222-0033 japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #15-08/10 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei, taiwan 114, r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-141 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760 ..

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